1. Field of the Invention
The present invention relates to an elastic store circuit for absorbing the propagation delay time difference among plural pieces of data transmitted through different transmission lines.
2. Description of the Related Prior Art
For example, assume that optical fiber capable of transmitting data of a maximum of 2.4 Gbps is used in a section of an optical fiber transmission line through which data of 10 Gbps is transmitted. First, data of 10 Gbps is divided into four pieces of data of 2.4 Gbps, and then the data of 10 Gbps is to be restored from the four pieces of data of 2.4 Gbps. If the four pieces of data of 2.4 Gbps are transmitted through different transmission lines, then there arise propagation time differences among the four pieces of data based on the variance of each transmission line. In this case, an elastic store circuit is required to absorb the propagation delay time difference.
FIG. 1 shows an example of a public elastic store circuit. The circuit includes a clock selector 4, a frame pulse retiming circuit 8, four frame counters 9, a detection circuit 10, and a read address counter 7. The data of 2.4 Gbps transmitted through four transmission lines are converted from optical signals to electric signals, and provided with clock and frame pulses. Since these four pieces of data of 2.4 Gbps are asynchronous to one another, it is necessary for the elastic store circuit to set these pieces of data in a synchronous state.
The operation of the circuit shown in FIG. 1 is described below. The clock selector 4 optionally selects a read clock of elastic store memory 6 from among the four asynchronous clocks. The frame pulse retiming circuit 8 retimes the four frame pulses indicating the MSB (most significant bit) by the read clock optionally selected by the clock selector 4. The retiming operations are completely asynchronous. The frame pulse after the retiming operation is used as a load pulse of the frame counter 9. Each of the frame counters 9 is initialized in the receipt order of the frame pulses, and each frame counter 9 starts counting data of 2.4 Gbps by the clock selected by the clock selector 4. The detection circuit 10 compares the count values of the four frame counters, and determines that the data having the minimum count value for a predetermined time is the data of 2.4 Gbps which arrived last. The output based on the determination result is a load pulse of the read address counter 7 of the elastic store memory 6. Therefore, the read phase of the elastic store memory 6 is determined based on the data of 2.4 Gbps having the longest propagation delay time. As a result, the propagation delay time differences among the four pieces of data of 2.4 Gbps are absorbed, thereby successfully restoring the data of 10 Gbps.
However, the above mentioned elastic store circuit includes, for example, four frame counters for counting one frame (125 μsec) of the SONET/SDH frame format, and compares the count values of the respective frame counters. Therefore, the circuit is complicated and large, and requires large power consumption. Furthermore, the circuit retimes four asynchronous frame pulses using one clock so as to realize the synchronous operations of four pieces of data of 2.4 Gbps. However, the frame pulse is normally a single pulse of 1 clock width. When the retiming phases for retiming frame pulses are asynchronous to one another, the output of the retiming flip-flop circuit falls in a metastable state, and the frame pulses having a single clock width are not correctly retimed.